Sciweavers

122 search results - page 1 / 25
» Distributed Reorder Buffer Schemes for Low Power
Sort
View
ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 1 months ago
Distributed Reorder Buffer Schemes for Low Power
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad ...
TVLSI
2008
96views more  TVLSI 2008»
13 years 4 months ago
Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors
Recently we proposed a new clocking scheme, injection-locked clocking (ILC), to combat deteriorating clock skew and jitter, and hence reduce power consumption in highperformance mi...
Lin Zhang, A. Carpenter, Berkehan Ciftcioglu, Alok...
HPCA
2005
IEEE
14 years 5 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...
CF
2008
ACM
13 years 7 months ago
Low power microarchitecture with instruction reuse
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power...
Frederico Pratas, Georgi Gaydadjiev, Mladen Bereko...
EUC
2006
Springer
13 years 8 months ago
Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB
- Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low powerconsumption, but also high comp...
Wann-Yun Shieh, Hsin-Dar Chen