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» Distributed sleep transistor network for power reduction
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HPCA
2009
IEEE
14 years 6 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
ICETET
2009
IEEE
13 years 3 months ago
High Performance WDM Using Semiconductor Tunable Laser
Advances in optical networking have lead to the explosive growth of communication network. Telecom applications began to drive significant investments into this field to support t...
S. S. Agrawal, K. D. Kulat, M. B. Daigavane
SPAA
2009
ACM
14 years 6 months ago
The weakest failure detector for wait-free dining under eventual weak exclusion
Dining philosophers is a classic scheduling problem for local mutual exclusion on arbitrary conflict graphs. We establish necessary conditions to solve wait-free dining under even...
Srikanth Sastry, Scott M. Pike, Jennifer L. Welch
COMCOM
2007
136views more  COMCOM 2007»
13 years 5 months ago
Demand-scalable geographic multicasting in wireless sensor networks
In this paper, we focus on the challenge of demand-scalable multicast routing in wireless sensor networks. Due to the ad-hoc nature of the placement of the sensor nodes as well as...
Shibo Wu, K. Selçuk Candan
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 5 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri