173 search results - page 1 / 35 » Domain Reduction for the Circuit Constraint |
CP
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. We present an incomplete filtering algorithm for the circuit constraint. The filter removes redundant values by eliminating nonHamiltonian edges from the associated gra...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
ESSCIRC
2011
12 years 4 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...