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» Dual-Channel Access Mechanism for Cost-Effective NoC Design
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DAC
2008
ACM
14 years 6 months ago
On reliable modular testing with vulnerable test access mechanisms
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
Lin Huang, Feng Yuan, Qiang Xu
IESS
2007
Springer
120views Hardware» more  IESS 2007»
13 years 11 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
BMCBI
2008
113views more  BMCBI 2008»
13 years 5 months ago
SNPFile - A software library and file format for large scale association mapping and population genetics studies
Background: High-throughput genotyping technology has enabled cost effective typing of thousands of individuals in hundred of thousands of markers for use in genome wide studies. ...
Jesper Nielsen, Thomas Mailund
ICCAD
2000
IEEE
95views Hardware» more  ICCAD 2000»
13 years 9 months ago
Test of Future System-on-Chips
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
Yervant Zorian, Sujit Dey, Mike Rodgers