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ERSA
2009
185views Hardware» more  ERSA 2009»
13 years 2 months ago
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
Mariusz Grad, Christian Plessl
AADEBUG
2005
Springer
13 years 10 months ago
Tdb: a source-level debugger for dynamically translated programs
Debugging techniques have evolved over the years in response to changes in programming languages, implementation techniques, and user needs. A new type of implementation vehicle f...
Naveen Kumar, Bruce R. Childers, Mary Lou Soffa
CGO
2003
IEEE
13 years 10 months ago
Retargetable and Reconfigurable Software Dynamic Translation
Software dynamic translation (SDT) is a technology that permits the modification of an executing program’s instructions. In recent years, SDT has received increased attention, f...
Kevin Scott, Naveen Kumar, S. Velusamy, Bruce R. C...
CGO
2006
IEEE
13 years 11 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
LCTRTS
2009
Springer
13 years 11 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...