29 search results - page 2 / 6 » Dynamic Co-Processor Architecture for Software Acceleration ... |
DAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
ISPASS
2006
IEEE
13 years 11 months ago
2006
IEEE
Detailed microarchitectural simulators are not well suited for exploring large design spaces due to their excessive simulation times. We introduce AXCIS, a framework for fast and ...
CASES
2009
ACM
13 years 11 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
CASES
2005
ACM
13 years 6 months ago
2005
ACM
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...