11 search results - page 1 / 3 » Dynamic Decimal Adder Circuit Design by using the Carry Look... |
DDECS
2006
IEEE
13 years 11 months ago
2006
IEEE
- This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the p...
CIT
2006
Springer
13 years 9 months ago
2006
Springer
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
The main result of this paper is the development of a low depth carry lookahead addition technique based on threshold logic. Two such adders are designed using the recently propos...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...