20 search results - page 2 / 4 » Dynamic Dictionary-Based Data Compression for Level-1 Caches |
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
Dynamic Zero Compression reduces the energy required for cache accesses by only writing and reading a single bit for every zero-valued byte. This energy-conscious compression is i...
ICPP
2003
IEEE
13 years 10 months ago
2003
IEEE
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
TVLSI
2010
13 years 12 hour ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
SIGCOMM
1997
ACM
13 years 9 months ago
1997
ACM
Caching in the World Wide Web currently follows a naive model, which assumes that resources are referenced many times between changes. The model also provides no way to update a c...