1815 search results - page 3 / 363 » Dynamic Power Management Using Data Buffers |
ANCS
2007
ACM
13 years 9 months ago
2007
ACM
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
ISCAS
2011
IEEE
2011
IEEE
Parallel Dynamic Voltage and Frequency Scaling for stream decoding using a multicore embedded system
12 years 9 months ago
—Parallel structures may be used to increase a system processing speed in case of large amount of data or highly complex calculations. Dynamic Voltage and Frequency Scaling (DVFS...
ICPP
1998
IEEE
13 years 10 months ago
1998
IEEE
We address the problems of I/O scheduling and buffer management for general reference strings in a parallel I/O system. Using the standard parallel disk model withD disks and a sh...
INFOCOM
2010
IEEE
13 years 4 months ago
2010
IEEE
—In recent years, the famous wiretap channel has been revisited by many researchers and information theoretic secrecy has become an active area of research in this setting. In th...
ICASSP
2010
IEEE
13 years 6 months ago
2010
IEEE
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient managem...