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ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
13 years 8 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
ISBI
2004
IEEE
14 years 6 months ago
Detection of Functional Networks In The Resting Brain
Recently, increasing attention has focused on exploring brain activity during rest. A current challenge is to ascertain activity patterns without using an external reference. In t...
Yong He, Yufeng Zang, Tianzi Jiang, Yingli Lu, Xuc...
VLSID
2005
IEEE
255views VLSI» more  VLSID 2005»
14 years 5 months ago
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. ...
PPOPP
2003
ACM
13 years 10 months ago
Exploiting high-level coherence information to optimize distributed shared state
InterWeave is a distributed middleware system that supports the sharing of strongly typed, pointer-rich data structures across a wide variety of hardware architectures, operating ...
DeQing Chen, Chunqiang Tang, Brandon Sanders, Sand...
CGF
2008
168views more  CGF 2008»
13 years 5 months ago
Interactive Global Illumination for Deformable Geometry in CUDA
Interactive global illumination for fully deformable scenes with dynamic relighting is currently a very elusive goal in the area of realistic rendering. In this work we propose a ...
Arne Schmitz, Markus Tavenrath, Leif Kobbelt