Sciweavers

74 search results - page 3 / 15
» Dynamic Reallocation of Functional Units in Superscalar Proc...
Sort
View
ICFEM
2010
Springer
13 years 4 months ago
Dynamic Resource Reallocation between Deployment Components
Abstract. Today’s software systems are becoming increasingly configurable and designed for deployment on a plethora of architectures, ranging from sequential machines via multic...
Einar Broch Johnsen, Olaf Owe, Rudolf Schlatte, Si...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
13 years 9 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
HPCA
2006
IEEE
14 years 5 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
INFOVIS
1999
IEEE
13 years 9 months ago
Visualizing Application Behavior on Superscalar Processors
The advent of superscalar processors with out-of-order execution makes it increasingly difficult to determine how well an application is utilizing the processor and how to adapt t...
Chris Stolte, Robert Bosch, Pat Hanrahan, Mendel R...
ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
14 years 2 months ago
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...
Santithorn Bunchua, D. Scott Wills, Linda M. Wills