CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit

Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimaera, a prototype system that integrates a small and fast reconfigurable functional unit (RFU) into the pipeline of an aggressive, dynamically−scheduled superscalar processor. Chimaera is capable of performing 9−input/1−output operations on integer data. We discuss the Chimaera C compiler that automatically maps computations for execution in the RFU. Chimaera is capable of: (1) collapsing a set of instructions into RFU operations, (2) converting control−flow into RFU operations, and (3) supporting a more powerful fine−grain data−parallel model than that supported by current multimedia extension instruction sets (for integer operations). Using a set of multimedia and communication applications we show that even with simple optimizations, the Chimaera C compiler is able to map 22% of all instructions ...

• Type: Conference
• Year: 2000
• Where: ISCA
• Authors: Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee
• Keywords: Chimaera, Hardware, ISCA 2000, RFU Operations, Superscalar Processor