Sciweavers

35 search results - page 1 / 7
» Dynamic configuration steering for a reconfigurable supersca...
Sort
View
IPPS
2005
IEEE
13 years 10 months ago
Configuration Steering for a Reconfigurable Superscalar Processor
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
Brian F. Veale, John K. Antonio, Monte P. Tull
IPPS
2006
IEEE
13 years 11 months ago
Dynamic configuration steering for a reconfigurable superscalar processor
A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous wor...
Nick A. Mould, Brian F. Veale, Monte P. Tull, John...
IPPS
2008
IEEE
13 years 11 months ago
Design of steering vectors for dynamically reconfigurable architectures
An architectural framework is studied that can perform dynamic reconfiguration. A basic objective is to dynamically reconfigure the architecture so that its configuration is well ...
Nick A. Mould, Brian F. Veale, John K. Antonio, Mo...
ERSA
2009
91views Hardware» more  ERSA 2009»
13 years 2 months ago
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors
Configuration with Self-configured Data Path (CSDP) is a high speed configuration data loading method for Dynamically Reconfigurable Processors (DRPs). By using a prepared configu...
Toru Sano, Yoshiki Saito, Hideharu Amano
IPPS
2000
IEEE
13 years 9 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi