6 search results - page 1 / 2 » Dynamic operand transformation for low-power multiplier-accu... |
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
: The design of portable battery-operated devices requires low-power computation circuits. This paper presents a new multiplier-accumulator (MAC) design approach, which in contrast...
ASAP
2008
IEEE
13 years 11 months ago
2008
IEEE
NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an alternative to RSA and ECC. This work presents a compact and low power NTRU design ...
HPCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
PLDI
1994
ACM
13 years 8 months ago
1994
ACM
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...