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HPCA
2005
IEEE
13 years 10 months ago
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increas...
Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai H...
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
13 years 10 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 5 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
DCOSS
2006
Springer
13 years 8 months ago
Network Power Scheduling for TinyOS Applications
This paper presents a study of the Flexible Power Scheduling protocol and evaluates its use for real-world sensor network applications and their platforms. FPS uses dynamically cre...
Barbara Hohlt, Eric A. Brewer
PERCOM
2005
ACM
14 years 4 months ago
Trading Latency for Energy in Wireless Ad Hoc Networks Using Message Ferrying
Power management is a critical issue in wireless ad hoc networks where the energy supply is limited. In this paper, we investigate a routing paradigm, Message Ferrying (MF), to sa...
Hyewon Jun, Wenrui Zhao, Mostafa H. Ammar, Ellen W...