Replacing global wires with an on-chip network: a power analysis

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Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and voltage scaling, to significantly reduce the energy to send a bit across chip. We develop an analytic model of large chip designs with an on-chip twodimensional mesh network and estimate the power savings possible in a 70 nm process for two different design points: a circuitswitched ASIC or FPGA design, and a dynamic packet-switched tiled architecture. For circuit-switched networks, achievable power savings are 35–50% for a mesh with 1 mm links. The packet switched designs use multiplexing and signal encoding to reduce the number of link wires required, but the router overhead limits peak wire power savings to around 20% with optimal tile sizes of around 2 mm. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles–Advanced Technologies, Microprocessors and Microcomputers, VL...
Seongmoo Heo, Krste Asanovic
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Authors Seongmoo Heo, Krste Asanovic
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