26 search results - page 1 / 6 » Dynamically Exploiting Narrow Width Operands to Improve Proc... |
HPCA
1999
IEEE
13 years 9 months ago
1999
IEEE
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
HPCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
CGO
2004
IEEE
13 years 9 months ago
2004
IEEE
Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method fo...
MICRO
2002
IEEE
13 years 10 months ago
2002
IEEE
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...