3 search results - page 1 / 1 » ECO algorithms for removing overlaps between power rails and... |
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
Design ECO commonly happens in industry due to constraints or target changes from manufacturing, marketing, reliability, or performance. At each step, designers usually want to mo...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
ICCD
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...