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DATE
2008
IEEE
107views Hardware» more  DATE 2008»
13 years 11 months ago
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints
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Chun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, M...
IPPS
2003
IEEE
13 years 10 months ago
Global Communication Optimization for Tensor Contraction Expressions under Memory Constraints
The accurate modeling of the electronic structure of atoms and molecules involves computationally intensive tensor contractions involving large multi-dimensional arrays. The effi...
Daniel Cociorva, Xiaoyang Gao, Sandhya Krishnan, G...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
13 years 8 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
13 years 9 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
IEEEPACT
2002
IEEE
13 years 9 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...