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MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
13 years 11 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
ASPLOS
2008
ACM
13 years 7 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
KDD
2004
ACM
138views Data Mining» more  KDD 2004»
14 years 5 months ago
IDR/QR: an incremental dimension reduction algorithm via QR decomposition
Dimension reduction is a critical data preprocessing step for many database and data mining applications, such as efficient storage and retrieval of high-dimensional data. In the ...
Jieping Ye, Qi Li, Hui Xiong, Haesun Park, Ravi Ja...
LCTRTS
2007
Springer
13 years 11 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
CCS
2006
ACM
13 years 9 months ago
EXE: automatically generating inputs of death
This paper presents EXE, an effective bug-finding tool that automatically generates inputs that crash real code. Instead of running code on manually or randomly constructed input,...
Cristian Cadar, Vijay Ganesh, Peter M. Pawlowski, ...