25 search results - page 1 / 5 » Efficient Hardware Controller Synthesis for Synchronous Data... |
ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
ISSS
1999
IEEE
13 years 9 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
RSP
1999
IEEE
13 years 9 months ago
1999
IEEE
Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes...
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes a new efficient buffer management technique called shift buffering for automatic code synthesis from synchronous dataflow graphs (SDF). Two previous buffer man...