279 search results - page 2 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
: In this paper, we present a point-to-point (P2P) communication synthesis methodology for SystemOn-Chip (SOC) design. We consider real-time systems where IP selection, mapping and...
INTEGRATION
2008
13 years 5 months ago
2008
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
ISLPED
2007
ACM
13 years 6 months ago
2007
ACM
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...
AC
2005
Springer
13 years 5 months ago
2005
Springer
Reducing power consumption has become a major challenge in the design and operation of today's computer systems. This chapter describes different techniques addressing this c...
DAC
2011
ACM
12 years 5 months ago
2011
ACM
In this paper, a new sparse approximation technique is proposed for incremental power grid analysis. Our proposed method is motivated by the observation that when a power grid net...