12 search results - page 2 / 3 » Efficient Scheduling of DSP Code on Processors with Distribu... |
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
CASES
2006
ACM
13 years 9 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
IEEEPACT
2000
IEEE
13 years 9 months ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
PPL
2006
13 years 5 months ago
2006
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
CASES
2006
ACM
13 years 11 months ago
2006
ACM
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...