16 search results - page 1 / 4 » Efficient Tree Layout in a Multilevel Memory Hierarchy |
CORR
2002
Springer
13 years 4 months ago
2002
Springer
CORR
2004
Springer
13 years 4 months ago
2004
Springer
Consider laying out a fixed-topology tree of N nodes into external memory with block size B so as to minimize the worst-case number of block memory transfers required to traverse ...
CGF
2006
13 years 4 months ago
2006
We present a novel algorithm to compute cache-efficient layouts of bounding volume hierarchies (BVHs) of polygonal models. Our approach does not make any assumptions about the cac...
TVCG
2010
12 years 11 months ago
2010
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...
MICRO
1997
IEEE
13 years 8 months ago
1997
IEEE
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...