3 search results - page 1 / 1 » Efficient Verification of Hazard-Freedom in Gate-Level Timed... |
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
ASYNC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
ICCAD
2006
IEEE
13 years 11 months ago
2006
IEEE
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...