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ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 3 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
APSCC
2010
IEEE
13 years 3 months ago
A Multicore-Aware Runtime Architecture for Scalable Service Composition
Middleware for web service orchestration, such as runtime engines for executing business processes, workflows, or web service compositions, can easily become performance bottleneck...
Daniele Bonetta, Achille Peternier, Cesare Pautass...
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 1 hour ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
BROADNETS
2007
IEEE
13 years 11 months ago
On supporting high quality 3D geometry multicasting over IEEE 802.11 wireless networks
—With significant improvements in both wireless technologies and computational capabilities of mobile devices, it is now possible to exchange and render 3D graphics over wireless...
Hui Li, Ming Li, B. Prabhakaran
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 2 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...