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» Efficient checker processor design
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MICRO
2007
IEEE
71views Hardware» more  MICRO 2007»
13 years 5 months ago
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning
Design complexity is rapidly becoming a limiting factor in the design of modern, high-performance microprocessors. This paper introduces an optimization technique to improve the e...
Francisco J. Mesa-Martinez, Jose Renau
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
13 years 11 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
CASES
2009
ACM
13 years 11 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
IOLTS
2003
IEEE
124views Hardware» more  IOLTS 2003»
13 years 10 months ago
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
The paper describes a specific method for designing selfchecking checkers for m-out-of-n codes. The method is oriented to the Field Programmable Gate Arrays technology and is base...
A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. N...
ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
13 years 10 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler