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» Efficient hardware code generation for FPGAs
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ASAP
2010
IEEE
193views Hardware» more  ASAP 2010»
13 years 7 months ago
Automatic generation of polynomial-based hardware architectures for function evaluation
Abstract--Polynomial approximation is a very general technique for the evaluation of a wide class of numerical functions of one variable. This article details an architecture gener...
Florent de Dinechin, Mioara Joldes, Bogdan Pasca
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
12 years 9 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
ISSS
1997
IEEE
102views Hardware» more  ISSS 1997»
13 years 9 months ago
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
Catherine H. Gebotys
IFIP12
2007
13 years 7 months ago
Hardware Natural Language Interface
In this paper an efficient architecture for natural language processing is presented, implemented in hardware using FPGAs (Field Programmable Gate Arrays). The system can receive s...
Christos Pavlatos, Alexandros C. Dimopoulos, Georg...
DATE
2010
IEEE
166views Hardware» more  DATE 2010»
13 years 10 months ago
A special-purpose compiler for look-up table and code generation for function evaluation
Abstract—Elementary functions are extensively used in computer graphics, signal and image processing, and communication systems. This paper presents a special-purpose compiler th...
Yuanrui Zhang, Lanping Deng, Praveen Yedlapalli, S...