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ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 5 months ago
A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
ISJGP
2010
13 years 2 months ago
On the Hardware Implementation Cost of Crypto-Processors Architectures
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
Nicolas Sklavos
MM
2009
ACM
217views Multimedia» more  MM 2009»
13 years 11 months ago
Streaming HD H.264 encoder on programmable processors
Programmable processors have great advantage over dedicated ASIC design under intense time-to-market pressure. However, realtime encoding of high-definition (HD) H.264 video (up t...
Nan Wu, Mei Wen, Wei Wu, Ju Ren, Huayou Su, Changq...
PATMOS
2004
Springer
13 years 10 months ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan