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CSREAESA
2006
13 years 6 months ago
Power Optimization of Interconnection Networks for Transport Triggered Architecture
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
Xue-mi Zhao, Zhiying Wang
CDES
2008
90views Hardware» more  CDES 2008»
13 years 6 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 2 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
ICPR
2008
IEEE
14 years 6 months ago
Unsupervised design of Artificial Neural Networks via multi-dimensional Particle Swarm Optimization
In this paper, we present a novel and efficient approach for automatic design of Artificial Neural Networks (ANNs) by evolving to the optimal network configuration(s) within an ar...
E. Alper Yildirim, Ince Turker, Moncef Gabbouj, Se...
DAC
2000
ACM
14 years 6 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf