26 search results - page 3 / 6 » Employing Register Channels for the Exploitation of Instruct... |
MICRO
1994
IEEE
13 years 10 months ago
1994
IEEE
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
ICS
1995
Tsinghua U.
13 years 9 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
MICRO
2005
IEEE
13 years 11 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
ICPP
2000
IEEE
13 years 10 months ago
2000
IEEE
Recently, the practice of speculation in resolving data dependences has been studied as a means of extracting more instruction level parallelism (ILP). An outcome of an instructio...
ICPP
2003
IEEE
13 years 11 months ago
2003
IEEE
Automatic optimization of address offset assignment for DSP applications, which reduces the number of address arithmetic instructions to meet the tight memory size restrictions an...