9 search results - page 1 / 2 » Enabling high-performance memory migration for multithreaded... |
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
As the number of cores per machine increases, memory architectures are being redesigned to avoid bus contention and sustain higher throughput needs. The emergence of Non-Uniform M...
ICMCS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
PPOPP
2010
ACM
14 years 2 months ago
2010
ACM
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
PVM
2010
Springer
13 years 3 months ago
2010
Springer
With the ever-increasing numbers of cores per node on HPC systems, applications are increasingly using threads to exploit the shared memory within a node, combined with MPI across ...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
—This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-...