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CAV
2004
Springer
151views Hardware» more  CAV 2004»
13 years 9 months ago
QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings
We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models--an important step during post-silicon verification of multipro...
Ganesh Gopalakrishnan, Yue Yang, Hemanthkumar Siva...
VLSID
2007
IEEE
153views VLSI» more  VLSID 2007»
14 years 5 months ago
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...
Zhaohui Fu, Sharad Malik
ICCAD
2009
IEEE
147views Hardware» more  ICCAD 2009»
13 years 2 months ago
SAT-based protein design
Computational protein design can be formulated as an optimization problem, where the objective is to identify the sequence of amino acids that minimizes the energy of a given prot...
Noah Ollikainen, Ellen Sentovich, Carlos Coelho, A...
JAIR
2006
179views more  JAIR 2006»
13 years 5 months ago
The Fast Downward Planning System
Fast Downward is a classical planning system based on heuristic search. It can deal with general deterministic planning problems encoded in the propositional fragment of PDDL2.2, ...
Malte Helmert