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IISWC
2008
IEEE
13 years 11 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood
ASPLOS
2006
ACM
13 years 11 months ago
A performance counter architecture for computing accurate CPI components
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, J...
EUROPAR
2005
Springer
13 years 11 months ago
PerfMiner: Cluster-Wide Collection, Storage and Presentation of Application Level Hardware Performance Data
Abstract. We present PerfMiner, a system for the transparent collection, storage and presentation of thread-level hardware performance data across an entire cluster. Every sub-proc...
Philip Mucci, Daniel Ahlin, Johan Danielsson, Per ...
AADEBUG
2005
Springer
13 years 11 months ago
Code coverage testing using hardware performance monitoring support
Code coverage analysis, the process of finding code exercised by a particular set of test inputs, is an important component of software development and verification. Most tradit...
Alex Shye, Matthew Iyer, Vijay Janapa Reddi, Danie...
DAC
1997
ACM
13 years 9 months ago
Static Timing Analysis of Embedded Software
This paper examines the problem of statically analyzing the performance of embedded software. This problem is motivated by the increasing growth of embedded systems and a lack of ...
Sharad Malik, Margaret Martonosi, Yau-Tsun Steven ...