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IMS
2000
115views Hardware» more  IMS 2000»
13 years 8 months ago
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Jose...
DELTA
2008
IEEE
13 years 6 months ago
Dynamic Co-operative Intelligent Memory
As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many met...
Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh
DAC
2006
ACM
14 years 6 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
13 years 8 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 8 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...