Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

10

IMS
2000

favoriteEmaildiscussreport

115views Hardware» more IMS 2000»

Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips

13 years 8 months ago

Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips

Download masc.soe.ucsc.edu

Michael C. Huang, Jose Renau, Seung-Moon Yoo, Jose

Real-time Traffic

Hardware | IMS 2000 |

claim paper

Related Content

» Dynamic Cooperative Intelligent Memory

» A Building Block for CoarseGrain Optimizations in the OnChip Memory Hierarchy

» A Framework for CoarseGrain Optimizations in the OnChip Memory Hierarchy

» NoCaware cache design for multithreaded execution on tiled chip multiprocessors

» Multiprocessor systemonchip data reuse analysis for exploring customized memory hierarchie...

» Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

» A thermallyaware performance analysis of vertically integrated 3D processormemory hierarch...

» The Energy Efficiency of IRAM Architectures

» Virtual hierarchies to support server consolidation

Post Info
More Details (n/a)

Added	25 Aug 2010
Updated	25 Aug 2010
Type	Conference
Year	2000
Where	IMS
Authors	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas

Comments (0)