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ICCD
1999
IEEE
80views Hardware» more  ICCD 1999»
13 years 9 months ago
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. P...
DCC
2008
IEEE
13 years 6 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
13 years 9 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
ICCD
2001
IEEE
84views Hardware» more  ICCD 2001»
14 years 1 months ago
Static Energy Reduction Techniques for Microprocessor Caches
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, S...
TVLSI
2010
12 years 11 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...