Sciweavers

3 search results - page 1 / 1
» Energy delay analysis of partial product reduction methods f...
Sort
View
ISLPED
1996
ACM
105views Hardware» more  ISLPED 1996»
13 years 9 months ago
Energy delay analysis of partial product reduction methods for parallel multiplier implementation
This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...
R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Kha...
APCCAS
2002
IEEE
157views Hardware» more  APCCAS 2002»
13 years 10 months ago
Multiplier energy reduction through bypassing of partial products
Designof portablebattery operatedmultimediadevices requires energy-ecient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital mul...
Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue
FPL
2009
Springer
99views Hardware» more  FPL 2009»
13 years 9 months ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne