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IPPS
2008
IEEE
13 years 11 months ago
Enhancing the effectiveness of utilizing an instruction register file
This paper describes the outcomes of the NSF Grant CNS-0615085: CSR-EHS: Enhancing the Effectiveness of Utilizing an Instruction Register File. We improved promoting instructions ...
David B. Whalley, Gary S. Tyson
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
13 years 8 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
13 years 8 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
HPCA
2005
IEEE
14 years 5 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
LCTRTS
2007
Springer
13 years 11 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...