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» Estimating design time for system circuits
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VLSI
2007
Springer
13 years 10 months ago
Estimating design time for system circuits
System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to estimate how much time it ...
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian G...
ICCAD
1994
IEEE
115views Hardware» more  ICCAD 1994»
13 years 8 months ago
Fast transient power and noise estimation for VLSI circuits
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
Wolfgang T. Eisenmann, Helmut E. Graeb
MJ
2007
119views more  MJ 2007»
13 years 4 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...
ICCAD
2006
IEEE
183views Hardware» more  ICCAD 2006»
14 years 1 months ago
Soft error derating computation in sequential circuits
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
Hossein Asadi, Mehdi Baradaran Tahoori
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
13 years 9 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin