710 search results - page 2 / 142 » Estimating design time for system circuits |
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
ICCD
1992
IEEE
13 years 9 months ago
1992
IEEE
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in ...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
—Presented are a methodology and a DFII-based tool for AC-stability analysis of a wide variety of closed-loop continuous-time (operational amplifiers and other linear circuits). ...
ASYNC
2002
IEEE
13 years 10 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
A closed form expression for the rise time of a gate driving a distributed RLC line is introduced that is within 8% of dynamic circuit simulations for a wide range of RLC loads. I...