710 search results - page 3 / 142 » Estimating design time for system circuits |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Variabilities in metal interconnect structures can affect circuit timing performance or even cause function failure in VLSI designs. This paper proposes a method to estimate the ...
SLIP
2003
ACM
13 years 10 months ago
2003
ACM
In the past, a priori interconnect prediction, based on Rent’s rule, has been applied mainly for technology evaluation and roadmap applications. These applications do not requir...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
According to the current trend of increasing variations in process technologies and thus in performance, the conservative worst-case design will not work since design margins can ...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...