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IEEEPACT
2008
IEEE
13 years 11 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
ISPASS
2003
IEEE
13 years 10 months ago
Accelerating private-key cryptography via multithreading on symmetric multiprocessors
Achieving high performance in cryptographic processing is important due to the increasing connectivity among today’s computers. Despite steady improvements in microprocessor and...
Praveen Dongara, T. N. Vijaykumar
IPPS
2005
IEEE
13 years 10 months ago
Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
Robert L. McGregor, Christos D. Antonopoulos, Dimi...
RTAS
2006
IEEE
13 years 11 months ago
Impact of Upper Layer Adaptation on End-to-end Delay Management in Wireless Ad Hoc Networks
A good amount of research has been developed to support QoS issues in IEEE 802.11 ad hoc networks, such as QoS routing, MAC layer QoS support, and cross-layer QoS design. However,...
Wenbo He, Klara Nahrstedt
ICDCS
2007
IEEE
13 years 11 months ago
Overlay Node Placement: Analysis, Algorithms and Impact on Applications
Abstract— Overlay routing has emerged as a promising approach to improving performance and reliability of Internet paths. To fully realize the potential of overlay routing under ...
Sabyasachi Roy, Himabindu Pucha, Zheng Zhang, Y. C...