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» Evaluation of Algorithms for Low Energy Mapping onto NoCs
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HPCA
2009
IEEE
14 years 5 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
ASPLOS
2012
ACM
12 years 16 days ago
Architecture support for disciplined approximate programming
Disciplined approximate programming lets programmers declare which parts of a program can be computed approximately and consequently at a lower energy cost. The compiler proves st...
Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug...
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
13 years 9 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan
GLOBECOM
2006
IEEE
13 years 11 months ago
Performance Analysis of Distributed Source Coding and Packet Aggregation in Wireless Sensor Networks
— In this paper, we propose a theoretical setup for evaluation of energy efficiency of wireless sensor networks (WSNs) with distributed source coding (DSC) algorithms and packet...
L. Di Paolo, Carlo Fischione, Carlo Graziosi, Fort...
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
11 years 7 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek