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FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
13 years 10 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
ANOR
2011
175views more  ANOR 2011»
13 years 24 days ago
Integrated exact, hybrid and metaheuristic learning methods for confidentiality protection
A vital task facing government agencies and commercial organizations that report data is to represent the data in a meaningful way and simultaneously to protect the confidentialit...
Fred Glover, Lawrence H. Cox, Rahul Patil, James P...
DAC
2009
ACM
14 years 6 months ago
ILP-based pin-count aware design methodology for microfluidic biochips
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
Cliff Chiung-Yu Lin, Yao-Wen Chang
COR
2007
80views more  COR 2007»
13 years 5 months ago
Scheduling with tool changes to minimize total completion time under controllable machining conditions
Scheduling under controllable machining conditions has been studied for some time. Scheduling with tool changes, particularly due to tool wear, has just begun to receive attention...
M. Selim Akturk, Jay B. Ghosh, Rabia K. Kayan
MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
13 years 11 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...