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» Executing Higher Order Logic
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FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
13 years 8 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
CASES
2010
ACM
13 years 3 months ago
Implementing virtual secure circuit using a custom-instruction approach
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
Zhimin Chen, Ambuj Sinha, Patrick Schaumont
SIGSOFT
2010
ACM
13 years 3 months ago
Language-based replay via data flow cut
A replay tool aiming to reproduce a program's execution interposes itself at an appropriate replay interface between the program and the environment. During recording, it log...
Ming Wu, Fan Long, Xi Wang, Zhilei Xu, Haoxiang Li...
CORR
2009
Springer
242views Education» more  CORR 2009»
13 years 3 months ago
Adaptive Scheduling of Data Paths using Uppaal Tiga
Abstract. We apply Uppaal Tiga to automatically compute adaptive scheduling strategies for an industrial case study dealing with a state-of-the-art image processing pipeline of a p...
Israa AlAttili, Fred Houben, Georgeta Igna, Steffe...
DEBU
2010
152views more  DEBU 2010»
13 years 2 months ago
Implementing an Append-Only Interface for Semiconductor Storage
Solid-state disks are currently based on NAND flash and expose a standard disk interface. To accommodate limitations of the medium, solid-state disk implementations avoid rewritin...
Colin W. Reid, Philip A. Bernstein