8 search results - page 1 / 2 » Experimental evaluation of a coarse-grained switch scheduler |
CSREAESA
2003
13 years 6 months ago
2003
− This paper presents an efficient system level power saving method for DRAM with multiple power modes. The proposed method is based on the power aware scheduling algorithm that ...
ANCS
2007
ACM
13 years 8 months ago
2007
ACM
Modern high performance routers rely on sophisticated interconnection networks to meet ever increasing demands on capacity. Previous studies have used a combination of analysis an...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
ICC
2009
IEEE
13 years 11 months ago
2009
IEEE
—In this paper we propose two advanced algorithms which allow for both differentiated quality-of-service (QOS) and power conservation in input-queued packet switches. These algor...
MASS
2010
13 years 2 months ago
2010
We study a problem in which a single sensor is scheduled to observe sites periodically, motivated by applications in which the goal is to maintain up-to-date readings for all the o...