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» Explaining Verification Conditions
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SIGSOFT
2004
ACM
14 years 5 months ago
PSE: explaining program failures via postmortem static analysis
In this paper, we describe PSE (Postmortem Symbolic Evaluation), a static analysis algorithm that can be used by programmers to diagnose software failures. The algorithm requires ...
Roman Manevich, Manu Sridharan, Stephen Adams, Man...
CAV
2009
Springer
157views Hardware» more  CAV 2009»
14 years 5 months ago
Explaining Counterexamples Using Causality
Abstract. When a model does not satisfy a given specification, a counterexample is produced by the model checker to demonstrate the failure. A user must then examine the counterexa...
Ilan Beer, Shoham Ben-David, Hana Chockler, Avigai...
PPDP
1999
Springer
13 years 9 months ago
Localizing and Explaining Reasons for Non-terminating Logic Programs with Failure-Slices
We present a slicing approach for analyzing logic programs with respect to non-termination. The notion of a failure-slice is presented which is an executable reduced fragment of th...
Ulrich Neumerkel, Frédéric Mesnard
CAV
2009
Springer
206views Hardware» more  CAV 2009»
14 years 5 months ago
D-Finder: A Tool for Compositional Deadlock Detection and Verification
D-Finder tool implements a compositional method for the verification of component-based systems described in BIP language encompassing multi-party interaction. For deadlock detecti...
Saddek Bensalem, Marius Bozga, Thanh-Hung Nguyen, ...
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
14 years 5 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...