87 search results - page 16 / 18 » Exploiting Postdominance for Speculative Parallelization |
APCSAC
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
ICPP
2009
IEEE
14 years 1 months ago
2009
IEEE
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
ISCAS
2005
IEEE
13 years 12 months ago
2005
IEEE
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
MICRO
1999
IEEE
13 years 10 months ago
1999
IEEE
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...