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» Exploiting Prediction to Reduce Power on Buses
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GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
13 years 11 months ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
13 years 11 months ago
A tunable bus encoder for off-chip data buses
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to red...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
JMLR
2010
117views more  JMLR 2010»
13 years 13 days ago
Exploiting the High Predictive Power of Multi-class Subgroups
Subgroup discovery aims at finding subsets of a population whose class distribution is significantly different from the overall distribution. A number of multi-class subgroup disc...
Tarek Abudawood, Peter A. Flach
IPPS
2007
IEEE
13 years 12 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
DATE
2005
IEEE
108views Hardware» more  DATE 2005»
13 years 11 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik